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DOC7707 bảng dữ liệu(PDF) 164 Page - List of Unclassifed Manufacturers

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Giải thích chi tiết về linh kiện  Microcontroller with 8/16K Bytes of ISP Flash and USB Controller
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DOC7707 bảng dữ liệu(HTML) 164 Page - List of Unclassifed Manufacturers

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7707F–AVR–11/10
AT90USB82/162
stop sending characters. RTS usage and so associated flow control is enabled using RTSEN bit
in UCSRnD.
Figure 17-8. shows a reception example.
Figure 17-8. Reception Flow Control Waveform Example
Figure 17-9. RTS behavior
RTS will rise at 2/3 of the last received stop bit if the receive fifo is full.
To ensure reliable transmissions, even after a RTS rise, an extra-data can still be received and
stored in the Receive Shift Register.
17.9.2
Transmission Flow Control
The transmission flow can be controlled by hardware using the CTS pin controlled by the exter-
nal receiver. The aim of the flow control is to stop transmission when the receiver is full of data
(CTS = 1). CTS usage and so associated flow control is enabled using CTSEN bit in UCSRnD.
The CTS pin is sampled at each CPU write and at the middle of the last stop bit that is
curently being sent.
Figure 17-10. CTS behavior
RTS
RXD
C1 C2
0
1
2
FIFO
1
CPU Read
Index
C3
1
0
RTS
RXD
Start
Byte0
Stop
Start
Byte1
Stop
Read from CPU
Start
Byte2
1 additional byte may be sent
if the transmitter misses the RTS trig
CTS
TXD
Start
Byte0
Stop
Start
Byte1
Stop
Start
Byte2
sample
sample
Write from CPU
sample



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