STM8L052C6 datasheet(74/102 Pages) STMICROELECTRONICS

74 / 102 page

Electrical parameters

STM8L052C6

74/102

Doc ID 023331 Rev 1

Table 35.

I/O static characteristics

Symbol

Parameter

Conditions(1)

Min

Typ

Max

Unit

VIL

Input low level voltage(2)

Input voltage on true open-drain

pins (PC0 and PC1)

VSS-0.3

0.3 x VDD

Input voltage on five-volt

tolerant (FT) pins (PA7 and

PE0)

VSS-0.3

0.3 x VDD

Input voltage on 3.6 V tolerant

(TT) pins

VSS-0.3

0.3 x VDD

Input voltage on any other pin

VSS-0.3

0.3 x VDD

VIH

Input high level voltage (2)

Input voltage on true open-drain

pins (PC0 and PC1)

with VDD < 2 V

0.70 x VDD

5.2

Input voltage on true open-drain

pins (PC0 and PC1)

with VDD ≥ 2 V

5.5

Input voltage on five-volt

tolerant (FT) pins (PA7 and

PE0)

with VDD < 2 V

0.70 x VDD

5.2

Input voltage on five-volt

tolerant (FT) pins (PA7 and

PE0)

with VDD ≥ 2 V

5.5

Input voltage on 3.6 V tolerant

(TT) pins

3.6

Input voltage on any other pin

0.70 x VDD

VDD+0.3

Vhys

Schmitt trigger voltage

hysteresis (3)

I/Os

200

True open drain I/Os

200

Ilkg

Input leakage current (4)

VSS≤ VIN≤ VDD

High sink I/Os

50 (5)

VSS≤ VIN≤ VDD

True open drain I/Os

200(5)

VSS≤ VIN≤ VDD

PA0 with high sink LED driver

capability

200(5)

RPU

Weak pull-up equivalent

resistor(2)(6)

VIN=VSS

CIO

I/O pin capacitance

VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.

Data based on characterization results, not tested in production.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

The max. value may be exceeded if negative current is injected on adjacent pins.

Not tested in production.

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