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AS3661 bảng dữ liệu(PDF) 54 Page - ams AG |
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AS3661 bảng dữ liệu(HTML) 54 Page - ams AG |
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54 / 87 page ![]() www.austriamicrosystems.com Revision 1.3 53 - 85 AS3661 Datasheet 5 STARTUP_BUSY 0 R A status bit which indicates that the device is running the internal start-up sequence. Please note that STARTUP_BUSY bit is always “1” when CHIP_EN bit is “0”. Please refer to section 8.5 for detailed startup mode description. 0: internal start-up sequence completed. 1: internal start-up sequence running. 4 ENGINE_BUSY 0 R A status bit which indicates that a program execution engine is clearing internal registers. Serial bus master should not write or read program memory, or registers 0x00, 0x37 to 0x39 or 0x4C to 0x4E, when this bit is set to "1". 0: engine ready. 1: at least one of the engines is clearing internal registers. 3 EXT_CLK_USED 0 R This bit is high when external clock signal on CLK pin is detected. CLK_DET_EN bit high in address 36 enables the clock detection. 0: external clock not detected. 1: external clock detected. 2 ENG1_INT 0 R This is the interrupt status bit for program execution engine 1. The bit is set by END or INT instruction. Reading the interrupt bit clears the interrupt. 0: interrupt unset/cleared. 1: interrupt set. 1 ENG2_INT 0 R This is the interrupt status bit for program execution engine 2. The bit is set by END or INT instruction. Reading the interrupt bit clears the interrupt. 0: interrupt unset/cleared. 1: interrupt set. 0 ENG3_INT 0 R This is the interrupt status bit for program execution engine 3. The bit is set by END or INT instruction. Reading the interrupt bit clears the interrupt. 0: interrupt unset/cleared. 1: interrupt set. Table 45. STATUS / INTERRUPT Register Register: 0x3A STATUS / INTERRUPT Bit Bit Name Default Access Bit Description |
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