AS3661 datasheet(12/87 Pages) AMSCO

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AS3661

Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s

tSU:STA

Setup Time for a

Repeated START

Condition

0.6

µs

tHD:DAT

Data Hold Time

tSU:DAT

Data Setup Time

100

Rise Time of Both

SDA and SCL Signals

20 +

0.1CB

300

Fall Time of Both SDA

and SCL Signals

15+

0.1CB

300

tSU:STO

Setup Time for STOP

Condition

0.6

µs

Capacitive Load for

Each Bus Line

Load of one Picofarad corresponds to one

nanosecond.

200

CI/O

I/O Capacitance

(SDA, SCL)

1. Specification is guaranteed by design and is not tested in production. VEN = 1.65V to VBAT.

2. After this period the first clock pulse is generated.

3. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the

SCL signal) to bridge the undefined region of the falling edge of SCL.

4. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then

be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a

device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max +

tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.

Table 4. Electrical Characteristics (Continued)I

Symbol

Parameter

Condition

Min

Typ

Max

Unit

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