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MPC8323E bảng dữ liệu(PDF) 16 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8323E
Giải thích chi tiết về linh kiện  PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
PDF  82 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC8323E bảng dữ liệu(HTML) 16 Page - Freescale Semiconductor, Inc

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
16
Freescale Semiconductor
DDR1 and DDR2 SDRAM
Figure 4 shows the input timing diagram for the DDR controller.
Figure 4. DDR Input Timing Diagram
6.2.2
DDR1 and DDR2 SDRAM Output AC Timing Specifications
Table 19 provides the output AC timing specifications for the DDR1 and DDR2 SDRAM interfaces.
Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with D
n_GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol1
Min
Max
Unit
Notes
MCK cycle time, (MCK/MCK crossing)
tMCK
7.5
10
ns
2
ADDR/CMD output setup with respect to MCK
tDDKHAS
ns
3
266 MHz
200 MHz
2.5
3.5
—
—
ADDR/CMD output hold with respect to MCK
tDDKHAX
ns
3
266 MHz
200 MHz
2.5
3.5
—
—
MCS output setup with respect to MCK
tDDKHCS
ns
3
266 MHz
200 MHz
2.5
3.5
—
—
MCS output hold with respect to MCK
tDDKHCX
ns
3
266 MHz
200 MHz
2.5
3.5
—
—
MCK to MDQS Skew
tDDKHMH
–0.6
0.6
ns
4
MCK[n]
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW



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