ADSP-21062LABZ-160 datasheet(12/64 Pages) AD

12 / 64 page

Rev. F

Page 12 of 64

March 2008

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

TFSx

I/O

Transmit Frame Sync (Serial Ports 0, 1).

RFSx

I/O

Receive Frame Sync (Serial Ports 0, 1).

LxDAT3–0

I/O

Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k

: internal pull-down resistor that is enabled or

disabled by the LPDRD bit of the LCOM register.

LxCLK

I/O

Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 k

: internal pull-down resistor that is enabled or

disabled by the LPDRD bit of the LCOM register.

LxACK

I/O

Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 k

: internal pull-down resistor that is

enabled or disabled by the LPDRD bit of the LCOM register.

EBOOT

EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-bit EPROM.

When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin

description below. This signal is a system configuration selection that should be hardwired.

LBOOT

Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When LBOOT is low,

the ADSP-2106x is configured for host processor booting or no booting. See the table in the BMS pin

description below. This signal is a system configuration selection that should be hardwired.

BMS

I/OT

Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1, LBOOT = 0).

In a multiprocessor system, BMS is output by the bus master.

Input: When low, indicates that no booting will

occur and that ADSP-2106x will begin executing instructions from external memory. See table below. This

input is a system configuration selection that should be hardwired. *Three-statable only in EPROM boot

mode (when BMS is an output).

EBOOT

LBOOT

BMS

Booting Mode

Output

EPROM (Connect BMS to EPROM chip select.)

1 (Input)

Host Processor

1 (Input)

Link Port

0 (Input)

No Booting. Processor executes from external memory.

0 (Input)

Reserved

x (Input)

Reserved

CLKIN

Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN. CLKIN should

not be halted, changed, or operated below the minimum specified frequency.

RESET

I/A

Processor Reset. Resets the ADSP-2106x to a known state and begins program execution at the program

memory location specified by the hardware reset vector address. This input must be asserted (low) at

power-up.

TCK

Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.

TMS

I/S

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k

: internal pull-up resistor.

TDI

I/S

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k

: internal pull-up

resistor.

TDO

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held

low for proper operation of the ADSP-2106x. TRST has a 20 k

: internal pull-up resistor.

EMU

Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.

ICSA

Reserved, leave unconnected.

VDD

Power Supply; nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins).

GND

Power Supply Return. (30 pins).

Do Not Connect. Reserved pins which must be left open and unconnected.

Table 3. Pin Descriptions (Continued)

Type

Function

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)

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