ADSP-21062LABZ-160 datasheet(32/64 Pages) AD

32 / 64 page

Rev. F

Page 32 of 64

March 2008

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Asynchronous Read/Write—Host to ADSP-2106x

Use these specifications for asynchronous host processor

accesses of an ADSP-2106x, after the host has asserted CS and

HBR (low). After HBG is returned by the ADSP-2106x, the host

can drive the RD and WR pins to access the ADSP-2106x’s

internal memory or IOP registers. HBR and HBG are assumed

low for this timing. Not required if and address are valid tHBGRCSV

after goes low. For first access after asserted, ADDR31–0 must

be a non-MMS value 1/2 tCLK before or goes low or by tHBGRCSV

after goes low. This is easily accomplished by driving an upper

address signal high when is asserted. See the “Host Processor

Control of the ADSP-2106x” section in the ADSP-2106x

SHARC User’s Manual, Revision 2.1.

Table 19. Read Cycle

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

tSADRDL

Address Setup/CS Low Before RD Low1

0ns

tHADRDH

Address Hold/CS Hold Low After RD

0ns

tWRWH

RD/WR High Width

tDRDHRDY

RD High Delay After REDY (O/D) Disable

tDRDHRDY

RD High Delay After REDY (A/D) Disable

Switching Characteristics

tSDATRDY

Data Valid Before REDY Disable from Low

tDRDYRDL

REDY (O/D) or (A/D) Low Delay After RD Low2

tRDYPRD

REDY (O/D) or (A/D) Low Pulse Width for Read

45 + 21DT/16

tHDARWH

Data Disable After RD High3

1 Not required if RD and address are valid t

HBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD or WR goes

low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the

ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1.

2 For ADSP-21060L, specification is 10.5 ns max; for ADSP-21060LC, specification is 12.5 ns max.

3 For ADSP-21060L/ADSP-21060LC, specification is 2 ns min, 8.5 ns max.

Table 20. Write Cycle

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

tSCSWRL

CS Low Setup Before WR Low

tHCSWRH

CS Low Hold After WR High

tSADWRH

Address Setup Before WR High

tHADWRH

Address Hold After WR High

tWWRL

WR Low Width

tWRWH

RD/WR High Width

tDWRHRDY

WR High Delay After REDY (O/D) or (A/D) Disable

tSDATWH

Data Setup Before WR High

tHDATWH

Data Hold After WR High

Switching Characteristics

tDRDYWRL

REDY (O/D) or (A/D) Low Delay After WR/CS Low

tRDYPWR

REDY (O/D) or (A/D) Low Pulse Width for Write

15 + 7DT/16

tSRDYCK

REDY (O/D) or (A/D) Disable to CLKIN

1 + 7DT/16

8 + 7DT/16

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