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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADSP-21062LABZ-160 bảng dữ liệu(PDF) 1 Page - Analog Devices |
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ADSP-21062LABZ-160 bảng dữ liệu(HTML) 1 Page - Analog Devices |
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1 / 64 page  SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. SHARC Processor ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel : 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. SUMMARY High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip Integrated multiprocessing features 240-lead thermally enhanced MQFP_PQ4 package, 225-ball plastic ball grid array (PBGA), 240-lead hermetic CQFP package RoHS compliant packages KEY FEATURES—PROCESSOR CORE 40 MIPS, 25 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Dual data address generators with modulo and bit-reverse addressing) Efficient program sequencing with zero-overhead looping: Single-cycle loop setup IEEE JTAG Standard 1149.1 Test Access Port and on-chip emulation 32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data format Figure 1. Functional Block Diagram MULT BARREL SERIAL PORTS (2) LINK PORTS (6) 4 6 6 36 IOP REGISTERS (MEMORY MAPPED) CONTROL, STATUS AND DATA BUFFERS I/O PROCESSOR TIMER INSTRUCTION CACHE ADDR DATA DATA ADDR ADDR DATA ADDR TWO INDEPENDENT DUAL-PORTED BLOCKS PROCESSOR PORT I/O PORT DUAL-PORTED SRAM JTAG TEST AND EMULATION 7 HOST PORT ADDR BUS MUX IOA 17 IOD 48 MULTIPROCESSOR INTERFACE EXTERNAL PORT DATA BUS MUX 48 32 24 DM ADDRESS BUS PM DATA BUS DM DATA BUS BUS CONNECT (PX) DAG1 32 48 40/32 CORE PROCESSOR PROGRAM SEQUENCER 8 4 32 DAG2 8 4 24 32 48-BIT PM ADDRESS BUS DATA CONTROLLER DMA DATA REGISTER FILE 16 40-BIT ALU SHIFTER S |
Số phần tương tự - ADSP-21062LABZ-160 |
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Mô tả tương tự - ADSP-21062LABZ-160 |
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