30F4013 datasheet(100/228 Pages) MICROCHIP

100 / 228 page

dsPIC30F3014/4013

DS70138G-page 100

 2010 Microchip Technology Inc.

15.2

Framed SPI Support

The module supports a basic framed SPI protocol in

Master or Slave mode. The control bit, FRMEN,

enables framed SPI support and causes the SSx pin to

perform the Frame Synchronization pulse (FSYNC)

function. The control bit, SPIFSD, determines whether

the SSx pin is an input or an output (i.e., whether the

module receives or generates the Frame Synchroniza-

tion pulse). The frame pulse is an active-high pulse for

a single SPI clock cycle. When Frame Synchronization

is enabled, the data transmission starts only on the

subsequent transmit edge of the SPI clock.

FIGURE 15-1:

SPI BLOCK DIAGRAM

FIGURE 15-2:

SPI MASTER/SLAVE CONNECTION

Note: x = 1 or 2.

Read

Write

Internal

Data Bus

SDIx

SDOx

SSx

SCKx

SPIxSR

SPIxBUF

bit 0

Shift

Clock

Edge

Select

Enable Master Clock

SSx and

Control

Clock

Control

Transmit

SPIxBUF

Receive

FSYNC

FCY

Primary

1:1, 1:4,

Prescaler

Secondary

Prescaler

1:1-1:8

1:16, 1:64

Serial Input Buffer

(SPIxBUF)

Shift Register

(SPIxSR)

MSb

LSb

SDOx

SDIx

PROCESSOR 1

SCKx

SPI Master

Serial Input Buffer

(SPIyBUF)

Shift Register

(SPIySR)

LSb

MSb

SDIy

SDOy

PROCESSOR 2

SCKy

SPI Slave

Serial Clock

Note: x = 1 or 2, y = 1 or 2.

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