30F4013 datasheet(51/228 Pages) MICROCHIP

51 / 228 page

 2010 Microchip Technology Inc.

DS70138G-page 51

dsPIC30F3014/4013

6.3

Writing to the Data EEPROM

To write an EEPROM data location, the following

sequence must be followed:

Erase the data EEPROM word.

Select the word, data EEPROM erase and

set the WREN bit in the NVMCON register.

Write the address of word to be erased into

NVMADR.

Enable the NVM interrupt (optional).

Write 0x55 to NVMKEY.

Write 0xAA to NVMKEY.

Set the WR bit. This begins the erase cycle.

Either poll the NVMIF bit or wait for the

NVMIF interrupt.

The WR bit is cleared when the erase cycle

ends.

Write the data word into data the EEPROM write

latches.

Program 1 data word into the data EEPROM.

Select the word, data EEPROM program and

set the WREN bit in the NVMCON register.

Enable the NVM write done interrupt

(optional).

Write 0x55 to NVMKEY.

Write 0xAA to NVMKEY.

Set the WR bit. This begins the program

cycle.

Either poll the NVMIF bit or wait for the

NVM interrupt.

The WR bit is cleared when the write cycle

ends.

The write does not initiate if the above sequence is not

exactly followed (write 0x55 to NVMKEY, write 0xAA to

NVMCON, then set WR bit) for each word. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in NVMCON must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

cution. The WREN bit should be kept clear at all times

except when updating the EEPROM. The WREN bit is

not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit does not affect the current write cycle. The

WR bit is inhibited from being set unless the WREN bit

is set. The WREN bit must be set on a previous instruc-

tion. Both WR and WREN cannot be set with the same

instruction.

At the completion of the write cycle, the WR bit is

cleared in hardware and the Nonvolatile Memory Write

Complete Interrupt Flag bit (NVMIF) is set. The user

may either enable this interrupt or poll this bit. NVMIF

must be cleared by software.

6.3.1

WRITING A WORD OF DATA

EEPROM

Once the user has erased the word to be programmed,

then a table write instruction is used to write one write

latch, as shown in Example 6-4.

6.3.2

WRITING A BLOCK OF DATA

EEPROM

To write a block of data EEPROM, write to all sixteen

latches first, then set the NVMCON register and

program the block, as shown in Example 6-5.

EXAMPLE 6-4:

DATA EEPROM WORD WRITE

; Point to data memory

MOV

#LOW_ADDR_WORD,W0

; Init pointer

MOV

#HIGH_ADDR_WORD,W1

MOV

W1,TBLPAG

MOV

#LOW(WORD),W2

; Get data

TBLWTL

W2,[ W0]

; Write data

; The NVMADR captures last table access address

; Select data EEPROM for 1 word op

MOV

#0x4004,W0

MOV

W0,NVMCON

; Operate key to allow write operation

DISI

; Block all interrupts with priority <7 for

; next 5 instructions

MOV

#0x55,W0

MOV

W0,NVMKEY

; Write the 0x55 key

MOV

#0xAA,W1

MOV

W1,NVMKEY

; Write the 0xAA key

BSET

NVMCON,#WR

; Initiate program sequence

NOP

; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle

; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete

30F4013 bảng dữ liệu(PDF) 51 Page - Microchip Technology

30F4013 bảng dữ liệu(HTML) 51 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL