30F4013 datasheet(88/228 Pages) MICROCHIP

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dsPIC30F3014/4013

DS70138G-page 88

 2010 Microchip Technology Inc.

13.5

Output Compare Operation During

CPU Sleep Mode

When the CPU enters Sleep mode, all internal clocks

are stopped. Therefore, when the CPU enters the

Sleep state, the output compare channel drives the pin

to the active state that was observed prior to entering

the CPU Sleep state.

For example, if the pin was high when the CPU entered

the Sleep state, the pin remains high. Likewise, if the

pin was low when the CPU entered the Sleep state, the

pin remains low. In either case, the output compare

module resumes operation when the device wakes up.

13.6

Output Compare Operation During

CPU Idle Mode

When the CPU enters the Idle mode, the output

compare module can operate with full functionality.

The output compare channel operates during the CPU

Idle mode if the OCSIDL bit (OCxCON<13>) is at logic

‘0’ and the selected time base (Timer2 or Timer3) is

enabled and the TSIDL bit of the selected timer is set

to logic ‘0’.

13.7

Output Compare Interrupts

The output compare channels have the ability to gener-

ate an interrupt on a compare match for whichever

Match mode has been selected.

For all modes, except the PWM mode, when a com-

pare event occurs, the respective interrupt flag (OCxIF)

is asserted and an interrupt is generated, if enabled.

The OCxIF bit is located in the corresponding IFSx reg-

ister and must be cleared in software. The interrupt is

enabled via the respective compare interrupt enable

(OCxIE) bit located in the corresponding IEC register.

For the PWM mode, when an event occurs, the respec-

tive Timer Interrupt Flag (T2IF or T3IF) is asserted and

an interrupt is generated, if enabled. The TxIF bit is

located in the IFS0 register and must be cleared in soft-

ware. The interrupt is enabled via the respective timer

interrupt enable bit (T2IE or T3IE) located in the IEC0

during the PWM mode of operation.

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