MCR03EZPFX1002 datasheet(15/33 Pages) IRF

15 / 33 page

Rev 16.0

PD-97509

IR3843AMPbF

Thermal Shutdown

Temperature

sensing

provided

inside

IR3843A. The trip threshold is typically set to

140oC. When trip threshold is exceeded, thermal

shutdown

turns

off

both

MOSFETs

and

discharges the soft start capacitor.

Automatic restart is initiated when the sensed

temperature drops within the operating range.

There is a 20oC hysteresis in the thermal

shutdown threshold.

Fig. 8b. Application Circuit for Simultaneous

Sequencing

Simultaneous Powerup

Vo1

Vo2

Output Voltage Sequencing

The

IR3843A

can

accommodate

user

programmable sequencing using Seq, Enable

and Power Good pins.

Boot

Vcc

Comp

Gnd

PGnd

OCSet

SS/ SD

4.5V <Vcc<5.5V

Vo(master)

PGood

Enable

1.5V <Vin<16V

Vin

Seq

Boot

Vcc

Comp

Gnd

PGnd

OCSet

SS/ SD

4.5V <Vcc<5.5V

Vo(slave)

PGood

Enable

1.5V <Vin<16V

Vin

Seq

Vo(master)

Fig. 8a. Simultaneous Power-up of the slave

with respect to the master.

Power Good Output

The IC continually monitors the output voltage via

Feedback (Fb pin). The feedback voltage forms

an input to a window comparator whose upper

and lower thresholds are 0.805V and 0.595V

respectively. Hence, the Power Good signal is

flagged when the Fb pin voltage is within the

PGood window, i. e., between 0.595V to 0.805V,

as shown in Fig .9 The PGood pin is open drain

and it needs to be externally pulled high. High

state indicates that output is in regulation. Fig. 9a

shows the PGood timing diagram for non-

tracking operation. In this case, during startup,

PGood goes high after the SS voltage reaches

2.1V if the Fb voltage is within the PGood

comparator window. Fig. 9a. and Fig 9.b. also

show a 256 cycle delay between the Fb voltage

entering within the thresholds defined by the

PGood window and PGood going high.

Through these pins, voltage sequencing such as

simultaneous

and

sequential

can

implemented. Figure 8. shows simultaneous

sequencing

configurations.

simultaneous

power-up, the voltage at the Seq pin of the slave

reaches 0.7V before the Fb pin of the master. For

E/RF =RC/RD, therefore, the output voltage of

the slave follows that of the master until the

voltage at the Seq pin of the slave reaches 0.7 V.

After the voltage at the Seq pin of the slave

exceeds 0.85V, the internal 0.7V reference of

the slave dictates its output voltage.

It is recommended that irrespective of the

sequencing configuration used, the input voltage

should be allowed to come up to its nominal

value first, followed by V

cc and Enable, before the

sequencing signal is applied.

For non-sequenced operation, the Seq pin

should be tied to a voltage greater than 0.85V,

such as 3.3V or V

cc. Again, the input voltage

should be allowed to come up before V

cc and

Enable.

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