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MCR03EZPFX1002 bảng dữ liệu(PDF) 17 Page - International Rectifier |
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MCR03EZPFX1002 bảng dữ liệu(HTML) 17 Page - International Rectifier |
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17 / 33 page ![]() Rev 16.0 17 PD-97509 IR3843AMPbF 70 75 80 85 90 95 300 400 500 600 700 800 900 1000 1100 1200 Switching Frequency (kHz) Minimum on time Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3843A, the typical minimum on-time is specified as 100 ns. Any design or application using the IR3843A must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 150 ns. This is necessary for the circuit to operate without jitter and pulse- skipping, which can cause high inductor current ripple and high output voltage ripple. In any application that uses the IR3843A, the following condition must be satisfied: The minimum output voltage is limited by the reference voltage and hence V out(min) = 0.7 V. Therefore, for V out(min) = 0.7 V, Therefore, even at the minimum switching frequency 250 kHz, no input voltage higher than 18.5V may be reliably converted down to 0.7V without excessive jitter or pulse skipping over the complete load range. In general, practical considerations dictate that any application that demands a pulse width smaller than 175ns may not exhibit jitter free operation over the entire load range. V/s . ns 150 V 0.7 V V in (min) (min) in 6 10 67 4 × = ≤ × ∴ ≤ × ∴ s on out s F t V F Maximum Duty Ratio Considerations A fixed off-time of 200 ns maximum is specified for the IR3843A. This provides an upper limit on the operating duty ratio at any given switching frequency. It is clear that, higher the switching frequency, the lower is the maximum duty ratio at which the IR3843A can operate. To allow a margin of 50ns, the maximum operating duty ratio in any application using the IR3843A should still accommodate about 250 ns off-time. Fig 10. shows a plot of the maximum duty ratio v/s the switching frequency, with 250 ns off-time. s out s on F V F D t Vin × = = (min) (min) (min) on out s in s in out on on on t V F V F V V t t t ≤ × ∴ × ≤ ∴ ≤ Fig. 10. Maximum duty cycle v/s switching frequency. |
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