MCR03EZPFX1002 datasheet(18/33 Pages) IRF

18 / 33 page

Rev 16.0

PD-97509

IR3843AMPbF

when an external resistor divider is connected to

the output as shown in figure 11.

Equation (7) can be rewritten as:

For the calculated values of R8 and R9 see

feedback compensation section.

Soft-Start Programming

The soft-start timing can be programmed by

selecting the soft-start capacitance value. From

(1), for a desired start-up time of the converter,

the soft start capacitor can be calculated by

using:

Where T

start is the desired start-up time (ms).

For a start-up time of 3.5ms, the soft-start

capacitor will be 0.099μF. Choose a 0.1μF

ceramic capacitor.

Bootstrap Capacitor Selection

To drive the Control FET, it is necessary to

supply a gate voltage at least 4V greater than

the voltage at the SW pin, which is connected

the source of the Control FET . This is achieved

by using a bootstrap configuration, which

comprises the internal bootstrap diode and an

external bootstrap capacitor (C6), as shown in

Fig .12. The operation of the circuit is as follows:

When the lower MOSFET is turned on, the

capacitor node connected to SW is pulled down

to ground. The capacitor charges towards V

through the internal bootstrap diode, which has a

forward voltage drop V

D. The voltage Vc across

the bootstrap capacitor C6 is approximately

given as

When the upper MOSFET turns on in the next

cycle, the capacitor node connected to SW rises

to the bus voltage V

in. However, if the value of

C6 is appropriately chosen,

Application Information

Design Example:

The following example is a typical application for

IR3843A. The application circuit is shown on

page 23.

Enabling the IR3843A

As explained earlier, the precise threshold of

the Enable lends itself well to implementation of

a UVLO for the Bus Voltage.

For a typical Enable threshold of V

EN = 1.2 V

For a V

in (min)=10.2V, R1=49.9K and R2=7.5K is a

good choice.

Programming the frequency

For F

s = 600 kHz, select Rt = 23.7 kΩ, using

Table. 1.

Output Voltage Programming

Output voltage is programmed by reference

voltage and external voltage divider. The Fb pin

is the inverting input of the error amplifier, which

is internally referenced to 0.7V. The divider is

ratioed to provide 0.7V at the Fb pin when the

output is at its desired value. The output voltage

is defined by using the following equation:

kHz

600

54mV

1.8

max)

13.2V

(

ΔV

≤

.....(7)

..........

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

∗

ref

Fig. 11. Typical application of the IR3843A for

programming the output voltage

(8)

....

..........

ref

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

∗

(10)

......

..........

−

≅

IR3624

VOUT

IR3843A

start

(9)

..........

0.02857

)

(

)

μF

(

IR3843A

Enable

Vin

(5)

..........

1.2

(min)

)

in(

(6)

..........

min

−

MCR03EZPFX1002 bảng dữ liệu(PDF) 18 Page - International Rectifier

MCR03EZPFX1002 bảng dữ liệu(HTML) 18 Page - International Rectifier

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

bảng dữ liệu tải về

Link URL