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JS28F512P30TFA bảng dữ liệu(PDF) 35 Page - Micron Technology |
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JS28F512P30TFA bảng dữ liệu(HTML) 35 Page - Micron Technology |
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35 / 86 page ![]() Datasheet Sept 2012 35 Order Number:208042-0 6 P30-65nm 11.2 Read Configuration Register (RCR) (Easy BGA) The RCR is a 16-bit read/write register used to select bus-read mode (synchronous or asynchronous), and to configure synchronous burst read characteristics of the device. To modify RCR settings, use the Configure Read Configuration Register command (see Section 6.2, “Device Command Bus Cycles” on page 20). RCR contents can be examined using the Read Device Identifier command, and then reading from offset 0x05 (see Section 7.2, “Read Device Identifier” on page 22). Upon power-up or exit from reset, the RCR defaults to asynchronous mode. The RCR is shown in Table 13. The following sections describe each RCR bit function. Table 13: Read Configuration Register Description (Sheet 1 of 2) Read Configuration Register (RCR) Read Mode Latency Count WAIT Polarity RES WAIT Delay Burst Seq CLK Edge RES RES Burst Wrap Burst Length RM LC[3:0] WP R WD BS CE R R BW BL[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 Read Mode (RM) 0 = Synchronous burst-mode read 1 = Asynchronous page-mode read (default) 14:11 Latency Count (LC[3:0]) 0011 =Code 3 0100 =Code 4 0101 =Code 5 0110 =Code 6 0111 =Code 7 1000 =Code 8 1001 =Code 9 1010 =Code 10 1011 =Code 11 1100 =Code 12 1101 =Code 13 1110 =Code 14 1111 =Code 15 (default) (Other bit settings are reserved) 10 WAIT Polarity (WP) 0 =WAIT signal is active low (default) 1 =WAIT signal is active high 9 Reserved (R) Default “0”, Non-changeable 8 WAIT Delay (WD) 0 =WAIT deasserted with valid data 1 =WAIT deasserted one data cycle before valid data (default) 7 Burst Sequence (BS) Default “0”, Non-changeable 6 Clock Edge (CE) 0 = Falling edge 1 = Rising edge (default) 5:4 Reserved (R) Reserved bits should be cleared (0) |
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