PCM1723ESLASH2K datasheet(13/21 Pages) TI

13 / 21 page

PCM1723

SBAS057A

www.ti.com

1024 system (= XTI) clocks

Reset

Reset Removal

2.6V

2.2V

1.8V

CC/VDD

Internal Reset

XTI Clock

FIGURE 14. RSTB-Pin Reset Timing.

1024 system (XTI) clocks

Reset

Reset Removal

XTI Clock

Internal Reset

RSTB

50% of V

RST

(1)

NOTE: (1) t

RST = 20ns min

FIGURE 13. Internal Power-On Reset Timing.

FIGURE 15. Latch-up Prevention Circuit.

POWER SUPPLY

CONNECTIONS

The PCM1723 has three power supply connections: digital

(VDD), analog (VCC), and PLL (VCP). Each connection also

has a separate ground return pin. It is acceptable to use a

common +5V power supply for all three power pins. If

separate supplies are used without a common connection,

the delta between the supplies during ramp-up time must be

less than 0.6V. An application circuit to avoid a power-on

latch-up condition is shown in Figure 15.

BYPASSING POWER SUPPLIES

The power supplies should be bypassed as close as

possible to the unit. Refer to Figure 18 for optimal values of

bypass capacitors. It is also recommended to include a

0.1

µF ceramic capacitor in parallel with the 10µF tantalum

capacitor.

DGND

AGND

Digital

Power Supply

Analog

Power Supply

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