PCM1723ESLASH2K datasheet(10/21 Pages) TI

10 / 21 page

PCM1723

SBAS057A

www.ti.com

OPE controls the operation of the DAC: when OPE is LOW,

the DAC will convert all non-zero input data. If the input

data is continuously zero for 65,536 cycles of BCKIN, the

output will be forced to zero only if IZD is HIGH. When

OPE is HIGH, the output of the DAC will be forced to

bipolar zero, irrespective of any input data.

IZD = 1

IZD = 0

DATA INPUT

DAC OUTPUT

Zero

Forced to BPZ(1)

Other

Normal

Zero

Zero(2)

Other

Normal

TABLE VI. Infinite Zero Detection (IZD) Function.

RSTB = HIGH

RSTB = LOW

SOFTWARE

MODE

DATA INPUT

DAC OUTPUT

INPUT

Zero

Controlled by OPE and IZD

Enabled

Other

Controlled by OPE and IZD

Enabled

Zero

Forced to BPZ(1)

Disabled

Other

Forced to BPZ(1)

Disabled

TABLE VII. Reset (RSTB) Function.

Bits 3 (IW0) and 4 (IW1) are used to determine input word

resolution. PCM1723 can be set up for input word resolu-

tions of 16, 20, or 24 bits:

Bit 4 (IW1)

Bit 3 (IW0)

Input Resolution

16-bit Data Word

20-bit Data Word

24-bit Data Word

Reserved

Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.

The output of PCM1723 can be programmed for 16 different

states, as shown in Table VIII.

PL0

PL1

PL2

PL3

Lch OUTPUT

Rch OUTPUT

NOTE

MUTE

(L + R)/2

MUTE

101

REVERSE

(L + R)/2

MUTE

STEREO

010

(L + R)/2

MUTE

(L + R)/2

MONO

TABLE VIII. Programmable Output Format.

B15 B14 B13 B12 B11 B10 B9

B8 B7

B1 B0

res

res res res res

IZD SF1 SF0 DSR1 DSR0 SYS ATC LRP I2S

attenuation channel control, system clock frequency, sam-

pling frequency, and infinite zero detection.

Bits 0 (I2S) and 1 (LRP) are used to control the input data

format. A LOW on bit 0 sets the format to Normal (MSB-

first, right-justified Japanese format), and a HIGH sets the

format to I2S (Philips serial data protocol). Bit 1 (LRP) is

used to select the polarity of LRCIN (sample rate clock).

When bit 1 is LOW, left channel data are assumed when

LRCIN is in a HIGH phase and right channel data are

assumed when LRCIN is in a LOW phase. When bit 1 is

HIGH, the polarity assumption is reversed.

Bit 2 (ATC) is used for controlling the attenuator. When

bit 2 is HIGH, the attenuation data loaded in program

bit 2 is LOW, the attenuation data for each register are

applied separately to left and right channels.

Bit 3 (SYS) is the system clock selection. When bit 3 is

LOW, the system clock frequency is set to 384fS. When bit

3 is HIGH, the system clock frequency is set to 256fS.

Bits 4 (DSR0) and 5 (DSR1) are used to control multiples

of the sampling rate:

DSR1

DSR0

Multiple

Normal

32/44.1/48kHz

Double

64/88.2/96kHz

One-half

16/22.05/24kHz

Reserved

Not Defined

Bits 6 (SF0) and 7 (SF1) are used to select the sampling

frequency. Frequency selection must be made with an

interval time greater than 20

µs.

SF1

SF0

Sampling Frequency

44.1kHz group

22.05/44.1/88.2kHz

48kHz group

24/48/96kHz

32kHz group

16/32/64kHz

Reserved

Not Defined

Bit 8 is used to control the infinite zero detection function

(IZD).

When IZD is LOW, the zero detect circuit is off. Under

this condition, no automatic muting will occur if the input

is continuously zero. When IZD is HIGH, the zero detect

feature is enabled. If the input data are continuously zero

for 65,536 cycles of BCKIN, the output will be immedi-

ately forced to a bipolar zero state (VCC/2). The zero

detection feature is used to avoid noise which may occur

when the input is DC. When the output is forced to bipolar

zero, there may be an audible click. PCM1723 allows the

zero detect feature to be disabled so the user can imple-

ment an external muting circuit.

NOTE: (1)

∆∑ is disconnected from output amplifier.

NOTES: (1)

∆∑ is disconnected from output amplifier.

(2)

∆∑ is connected to output amplifier.

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