PCM1723ESLASH2K datasheet(11/21 Pages) TI

11 / 21 page

PCM1723

SBAS057A

www.ti.com

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

ML (pin 6)

MC (pin 7)

MD (pin 8)

FIGURE 8. Three-Wire Serial Interface.

FIGURE 9. Program Register Input Timing.

APPLICATION

CONSIDERATIONS

DELAY TIME

There is a finite delay time in delta-sigma converters. In

analog-to-digital converters (ADCs), this is commonly re-

ferred to as latency. For a delta-sigma DAC, delay time is

determined by the order number of the FIR filter stage, and

the chosen sampling rate. The following equation expresses

the delay time of PCM1723:

tD = 11.125 x 1/fS

For fS = 44.1kHz, tD = 11.125/44.1kHz = 251.4µs

Applications using data from a disc or tape source, such as

CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc.,

generally are not affected by delay time. For some profes-

sional applications such as broadcast audio for studios, it is

important for total delay time to be less than 2ms.

OUTPUT FILTERING

For testing purposes all dynamic tests are done on the

PCM1723 using a 20kHz low-pass filter. This filter limits

the measured bandwidth for THD+N, etc. to 20kHz. Failure

to use such a filter will result in higher THD+N and lower

SNR and Dynamic Range readings than are found in the

specifications. The low-pass filter removes out of band

noise. Although it is not audible, it may affect dynamic

specification numbers.

MC Pulse Cycle Time

tMCY

100ns (min)

MC Pulse Width LOW

tMCL

50ns (min)

MC Pulse Width HIGH

tMCH

50ns (min)

MD Setup Time

tMDS

30ns (min)

MD Hold Time

tMDH

30ns (min)

ML Low Level Time

tMLL

30ns + 1SYSCLK (min)

ML High Level Time

tMLH

30ns + 1SYSCLK (min)

ML Setup Time

tMLS

30ns (min)

ML Hold Time

tMHH

30ns (min)

SYSCLK: 1/256fS or 1/384fS

1.4V

MLL

MHH

MCH

MCL

MDS

MCY

MLS

MLH

MDH

LSB

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