H3LIS331DL datasheet(24/38 Pages) STMICROELECTRONICS

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H3LIS331DL

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The device contains a set of registers which are used to control its behavior and to retrieve

acceleration data. The register address, consisting of 7 bits, is used to identify them and to

write the data through the serial interface.

7.1

WHO_AM_I (0Fh)

Device identification register.

This register contains the device identifier that for the H3LIS331DL is set to 32h.

7.2

CTRL_REG1 (20h)

The PM bits allow the user to select between power-down and two operating active modes.

The device is in power-down mode when the PD bits are set to “000” (default value after

boot). Table 19 shows all the possible power mode configurations and respective output

data rates. Output data in the low-power mode are computed with the low-pass filter cutoff

frequency defined by the DR1, DR0 bits.

The DR bits, in normal mode operation, select the data rate at which acceleration samples

are produced. In low-power modes they define the output data resolution. Table 20 shows

all the possible configurations for the DR1 and DR0 bits.

Table 16. WHO_AM_I register

00110010

Table 17. CTRL_REG1 register

PM2

PM1

PM0

DR1

DR0

Zen

Yen

Xen

Table 18. CTRL_REG1 description

PM2 - PM0

Power mode selection. Default value: 000

(000: power-down; Others: refer to Table 19)

DR1, DR0

Data rate selection. Default value: 00

(00:50 Hz; Others: refer to Table 20)

Zen

Z-axis enable. Default value: 1

(0: Z-axis disabled; 1: Z-axis enabled)

Yen

Y-axis enable. Default value: 1

(0: Y-axis disabled; 1: Y-axis enabled)

Xen

X-axis enable. Default value: 1

(0: X-axis disabled; 1: X-axis enabled)

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