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ST7FLITE25F2M6 bảng dữ liệu(PDF) 41 Page - STMicroelectronics |
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ST7FLITE25F2M6 bảng dữ liệu(HTML) 41 Page - STMicroelectronics |
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41 / 166 page  ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Supply, reset and clock management Doc ID 8349 Rev 5 41/166 The LVD Reset circuitry generates a reset when VDD is below: ● VIT+(LVD)when VDD is rising ● VIT-(LVD) when VDD is falling. The LVD function is illustrated in Figure 17. The voltage threshold can be configured by option byte to be low, medium or high. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: ● under full software control ● in static safe reset. In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Note: The LVD allows the device to be used without any external RESET circuitry. The LVD is an optional function which can be selected by option byte. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 84: RESET pin protection when LVD is enabled It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. Figure 17. Low voltage detector vs. Reset VDD VIT+(LVD) RESET VIT-(LVD) Vhys |
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