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ST7FLITE25F2M6 bảng dữ liệu(HTML) 71 Page - STMicroelectronics |
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71 / 166 page  ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 On-chip peripherals Doc ID 8349 Rev 5 71/166 11 On-chip peripherals 11.1 Watchdog timer (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared. 11.1.2 Main features ● Programmable free-running downcounter (64 increments of 16000 CPU cycles) ● Programmable reset ● Reset (if watchdog activated) when the T6 bit reaches zero ● Optional reset on HALT instruction (configurable by option byte) ● Hardware Watchdog selectable by option byte. 11.1.3 Functional description The counter value stored in the CR register (bits T[6:0]), is decremented every 16000 machine cycles, and the length of the time-out period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30 μs. Figure 33. Watchdog block diagram Reset WDGA 7-bit downcounter fCPU T6 T0 Clock divider Watchdog control register (CR) ÷16000 T1 T2 T3 T4 T5 |
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