AD5204BRUZ100-R7 datasheet(16/20 Pages) AD

16 / 20 page

AD5204/AD5206

Rev. C | Page 16 of 20

TEST CIRCUITS

340kΩ

VSS

LOGIC

Figure 25. ESD Protection of Digital Pins

A, B, W

VSS

Figure 26. ESD Protection of Resistor Terminals

V+

DUT

VMS

V+ = VDD

1LSB = V+/256

Figure 27. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)

DUT

VMS

NO CONNECT

Figure 28. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

V+

DUT

IMS

VMS

IW = 1V/RNOMINAL

V+

VDD

RW =

WHERE VW1 = VMS WHEN IW = 0

AND VW2 = VMS WHEN IW = 1/R

VW2 – [VW1 + IW(RAWII RBW)]

Figure 29. Wiper Resistance Test Circuit

V+

VMS

VDD

V+ = VDD ± 10%

PSRR (dB) = 20 log

∆VMS

∆VDD

PSS (%/%) =

∆VMS%

∆VDD%

(

)

Figure 30. Power Supply Sensitivity Test Circuit (PSS, PSRR)

VIN

OFFSET BIAS

OP279

VOUT

DUT

OFFSET

GND

Figure 31. Inverting Programmable Gain Test Circuit

VIN

OFFSET BIAS

OP279

VOUT

DUT

OFFSET

GND

Figure 32. Noninverting Programmable Gain Test Circuit

VIN

2.5V

+15V

VOUT

DUT

–15V

OFFSET

GND

OP42

Figure 33. Gain vs. Frequency Test Circuit

DUT

ISW

VSS TO VDD

RSW =

0.1V

ISW

CODE = 0x00

0.1V

–

Figure 34. Incremental On-Resistance Test Circuit

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