AD5204BRUZ100-R7 datasheet(15/20 Pages) AD

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AD5204/AD5206

Rev. C | Page 15 of 20

DIGITAL INTERFACING

The AD5204/AD5206 each contain a standard 3-wire serial

input control interface. The three inputs are clock (CLK), chip

select input (CS), and serial data input (SDI). The positive-

edge-sensitive CLK input requires clean transitions to avoid

clocking incorrect data into the serial input register. Standard

logic families work well. If mechanical switches are used for

product evaluation, they should be debounced by a flip-flop or

by other suitable means.

shows more detail of the

internal digital circuitry. When

Figure 22

CS is taken active low, the clock

loads data into the serial register on each positive clock edge

(see

). When using a positive (VDD) and negative (VSS)

supply voltage, the logic levels are still referenced to digital

ground (GND).

Table 9

The serial data output (SDO) pin contains an open-drain

n-channel FET. This output requires a pull-up resistor to transfer

data to the SDI pin of the next package. The pull-up resistor

termination voltage can be larger than the VDD supply of the

AD5204. For example, the AD5204 can operate at VDD = 3.3 V,

and the pull-up for the interface to the next device can be set at

5 V. This allows for daisy chaining several RDACs from a

single-processor serial data line.

If a pull-up resistor is used to connect the SDI pin of the

next device in the series, the clock period must be increased.

Capacitive loading at the daisy-chain node (where SDO and

SDI are connected) between the devices must be accounted for

to successfully transfer data. When daisy chaining is used, the

CS should be kept low until all the bits of every package are

clocked into their respective serial registers, ensuring that the

address bits and data bits are in the proper decoding locations.

This requires 22 bits of address and data complying to the data-

word format outlined in

if two AD5204 4-channel RDACs

are daisy-chained. During shutdown (

Table 6

SHDN), the SDO output

pin is forced to the off (logic high state) position to disable power

dissipation in the pull-up resistor. See

for the equivalent

SDO output circuit schematic.

Figure 24

Table 9. Input Logic Control Truth Table1

CLK

SHDN

No SR effect; enables SDO pin.

Shift one bit in from the SDI pin. The

11th bit entered is shifted out of the

SDO pin.

Load SR data into the RDAC latch

based on A2, A1, A0 decode (Table 10).

No operation.

Sets all RDAC latches to midscale;

wiper centered and SDO latch

cleared.

Latches all RDAC latches to 0x80.

Open circuits all A resistor terminals,

connects Wiper W to Terminal B, and

turns off the SDO output transistor.

1 P = positive edge, X = don’t care, SR = shift register.

Table 10. Address Decode Table

Latch Decoded

RDAC 1

RDAC 2

RDAC 3

RDAC 4

RDAC 5 AD5206 only

RDAC 6 AD5206 only

The data setup and data hold times in the specification table

determine the data valid time requirements. The last 11 bits of

the data-word entered into the serial register are held when CS

returns high. When CS goes high, the address decoder is gated,

enabling one of four or six positive-edge-triggered RDAC

latches (see

for details).

Figure 23

ADDR

DECODE

RDAC 1

RDAC 2

RDAC 4/

RDAC 6

SERIAL

AD5204/AD5206

SDI

CLK

Figure 23. Equivalent Input Control Logic

The target RDAC latch is loaded with the last eight bits of the

serial data-word, completing one DAC update. Four separate

8-bit data-words must be clocked in to change all four VR

settings.

SERIAL

SDI

CK RS

SHDN

CLK

SDO

GND

Figure 24. Detail SDO Output Schematic of the AD5204

All digital pins (CS, SDI, SDO, PR, SHDN, and CLK) are

protected with a series input resistor and a parallel Zener ESD

structure (see

Figure 25

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