M68ICS08GR datasheet(250/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

Technical Data

MC68HC908GR8 — Rev 4.0

250

Serial Communications Interface (SCI)

MOTOROLA

•

Framing error (FE) — The FE bit in SCS1 is set when a logic 0

occurs where the receiver expects a stop bit. The framing error

interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI

error CPU interrupt requests.

•

Parity error (PE) — The PE bit in SCS1 is set when the SCI

detects a parity error in incoming data. The parity error interrupt

enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU

interrupt requests.

18.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumption standby modes.

18.6.1 Wait Mode

The SCI module remains active after the execution of a WAIT

instruction. In wait mode, the SCI module registers are not accessible by

the CPU. Any enabled CPU interrupt request from the SCI module can

bring the MCU out of wait mode.

If SCI module functions are not required during wait mode, reduce power

consumption by disabling the module before executing the WAIT

instruction.

Refer to Low Power Modes for information on exiting wait mode.

18.6.2 Stop Mode

The SCI module is inactive after the execution of a STOP instruction.

The STOP instruction does not affect SCI register states. SCI module

operation resumes after an external interrupt.

Because the internal clock is inactive during stop mode, entering stop

mode during an SCI transmission or reception results in invalid data.

Refer to Low Power Modes for information on exiting stop mode.

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