M68ICS08GR datasheet(64/408 Pages) FREESCALE

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Resets and Interrupts

Technical Data

MC68HC908GR8 — Rev 4.0

Resets and Interrupts

MOTOROLA

4.3.3.3 Low-Voltage Inhibit Reset

A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in

the power supply voltage to the LVI trip voltage, VTRIPF.

An LVI reset:

•

Holds the clocks to the CPU and modules inactive for an oscillator

stabilization delay of 4096 CGMXCLK cycles after the power

supply voltage rises to VTRIPF

•

Drives the RST pin low for as long as VDD is below VTRIPF and

during the oscillator stabilization delay

•

Releases the RST pin 32 CGMXCLK cycles after the oscillator

stabilization delay

•

Releases the CPU to begin the reset vector sequence

64 CGMXCLK cycles after the oscillator stabilization delay

•

Sets the LVI bit in the SIM reset status register

4.3.3.4 Illegal Opcode Reset

An illegal opcode reset is an internal reset caused by an opcode that is

not in the instruction set. An illegal opcode reset sets the ILOP bit in the

SIM reset status register.

If the stop enable bit, STOP, in the mask option register is a logic 0, the

STOP instruction causes an illegal opcode reset.

4.3.3.5 Illegal Address Reset

An illegal address reset is an internal reset caused by opcode fetch from

an unmapped address. An illegal address reset sets the ILAD bit in the

SIM reset status register.

A data fetch from an unmapped address does not generate a reset.

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