TL16C554APNR datasheet(36/46 Pages) TI1

36 / 46 page

TL16C554A, TL16C554AI

ASYNCHRONOUS-COMMUNICATIONS ELEMENT

SLLS509E − AUGUST 2001 − REVISED JUNE 2010

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

scratchpad register

The scratchpad register is an 8-bit read/write register that has no effect on any ACE channel. It is intended to

be used by the programmer to hold data temporarily.

TXRDY operation

In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO

contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY is asserted (low).

In mode 1, TXRDY is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written

with another byte when TXRDY is asserted (low).

Driver

Optional

Driver

External

Clock

Optional

Clock

Output

Oscillator Clock

to Baud

Generator Logic

VCC

Crystal

Oscillator Clock

to Baud

Generator Logic

RX2

VCC

XTAL1

XTAL2

TYPICAL CRYSTAL OSCILLATOR NETWORK

CRYSTAL

RX2

3.1 MHz

1 M

1.5 k

10 − 30 pF

40 − 60 pF

1.8 MHz

1 M

1.5 k

10 − 30 pF

40 − 60 pF

Figure 24. Typical Clock Circuits

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