TL16C554APNR datasheet(26/46 Pages) TI1

26 / 46 page

TL16C554A, TL16C554AI

ASYNCHRONOUS-COMMUNICATIONS ELEMENT

SLLS509E − AUGUST 2001 − REVISED JUNE 2010

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

line-status register (LSR) (continued)

D Bit 4: LSR4 is the break interrupt (BI) bit. Break interrupt is set when the received data input is held in the

spacing (low) state for longer than a full word transmission time (start bit + data bits + parity + stop bits).

The BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated

with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the

FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the

first LSR read. Only one zero character is loaded into the FIFO when BI occurs.

LSR1 − LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the

interrupt-identification register) when any of the conditions are detected. This interrupt is enabled by setting

IER2 in the interrupt-enable register.

D Bit 5: LSR5 is the transmitter holding register empty (THRE) bit. THRE indicates that the ACE is ready to

accept a new character for transmission. The THRE bit is set when a character is transferred from the

transmitter holding register (THR) to the transmitter shift register (TSR). LSR5 is cleared when the CPU

loads THR. LSR5 is not cleared by a CPU read of the LSR. In the FIFO mode, this bit is set when the transmit

FIFO is empty, and it is cleared when one byte is written to the transmit FIFO. When the THRE interrupt

is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. If THRE is the interrupt source indicated

by IIR, INTRPT is cleared by a read of the IIR.

D Bit 6: LSR6 is the transmitter register empty (TEMT) bit. TEMT is set when both THR and TSR are empty.

LSR6 is cleared when a character is loaded into THR, and remains low until the character is transferred out

of TXx. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, this bit is set when both the

transmitter FIFO and shift register are empty.

D Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is cleared in the TL16C450 mode (see FCR bit 0).

In the FIFO mode, it is set when at least one of the following data errors is in the FIFO: parity error, framing

error, or break interrupt indicator. It is cleared when the CPU reads the LSR, unless there are subsequent

errors in the FIFO.

NOTE

The LSR may be written. However, this function is intended only for factory test. It should be considered as read

only by applications software.

Table 6. Line-Status Register BIts

LSR BITS

LSR0 data ready (DR)

Ready

Not ready

LSR1 overrun error (OE)

Error

No error

LSR2 parity error (PE)

Error

No error

LSR3 framing error (FE)

Error

No error

LSR4 break interrupt (BI)

Break

No break

LSR5 transmitter holding register empty (THRE)

Empty

Not empty

LSR6 transmitter register empty (TEMT)

Empty

Not empty

LSR7 receiver FIFO error

Error in FIFO

No error in FIFO

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