A32100DX datasheet(48/98 Pages) ACTEL

48 / 98 page

A3 21 00 DX Ti m i n g Ch ar ac te r i st i c s

(Wor s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)

‘–1’ Speed

‘Std’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

Logic Module Combinatorial Functions

tPD

Internal Array Module Delay

3.1

4.1

tPDD

Internal Decode Module Delay

3.3

4.3

Logic Module Predicted Routing Delays1

tRD1

FO=1 Routing Delay

1.3

1.8

tRD2

FO=2 Routing Delay

1.9

2.6

tRD3

FO=3 Routing Delay

2.6

3.4

tRD4

FO=4 Routing Delay

3.3

4.3

tRD5

FO=8 Routing Delay

0.6

0.8

tRDD

Decode-to-Output Routing Delay

0.5

0.6

Logic Module Sequential Timing

tCO

Flip-Flop Clock-to-Output

3.1

4.1

tGO

Latch Gate-to-Output

3.1

4.1

tSU

Flip-Flop (Latch) Setup Time

0.5

0.6

Flip-Flop (Latch) Hold Time

0.0

tRO

Flip-Flop (Latch) Reset to Output

3.1

4.1

tSUENA

Flip-Flop (Latch) Enable Setup

0.9

1.2

tHENA

Flip-Flop (Latch) Enable Hold

0.0

tWCLKA

Flip-Flop (Latch) Clock Active Pulse

Width

4.3

5.8

tWASYN

Flip-Flop (Latch) Asynchronous Pulse

Width

5.6

7.5

Note:

Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is

based on actual routing delay measurements performed on the device prior to shipment.

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