A32100DX datasheet(35/98 Pages) ACTEL

35 / 98 page

Hi R e l F P GA s

A1 28 0XL Ti m i ng Cha r act e r i s t i cs (continued)

(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)

‘–1’ Speed

‘Std’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

TTL Output Module Timing1

tDLH

Data to Pad High

5.3

6.2

tDHL

Data to Pad Low

5.7

6.6

tENZH

Enable Pad Z to High

5.3

6.2

tENZL

Enable Pad Z to Low

5.8

6.8

tENHZ

Enable Pad High to Z

7.5

8.9

tENLZ

Enable Pad Low to Z

7.5

8.9

tGLH

G to Pad High

5.9

6.9

tGHL

G to Pad Low

6.6

7.8

dTLH

Delta Low to High

0.05

0.06

ns/pF

dTHL

Delta High to Low

0.05

0.09

ns/pF

CMOS Output Module Timing1

tDLH

Data to Pad High

6.6

7.9

tDHL

Data to Pad Low

4.7

5.5

tENZH

Enable Pad Z to High

5.3

6.2

tENZL

Enable Pad Z to Low

5.8

6.8

tENHZ

Enable Pad High to Z

7.5

8.9

tENLZ

Enable Pad Low to Z

7.5

8.9

tGLH

G to Pad High

5.9

6.9

tGHL

G to Pad Low

6.6

7.8

dTLH

Delta Low to High

0.07

0.09

ns/pF

dTHL

Delta High to Low

0.06

0.09

ns/pF

Notes:

Delays based on 50 pF loading.

SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at

http://www.actel.com/appnotes.

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