A32100DX datasheet(29/98 Pages) ACTEL

29 / 98 page

Hi R e l F P GA s

A1 24 0A T i m i n g C har a c t e r i st i c s (continued)

(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)

‘–1’ Speed

‘Std’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Units

TTL Output Module Timing1

tDLH

Data to Pad High

11.0

13.0

tDHL

Data to Pad Low

13.9

16.4

tENZH

Enable Pad Z to High

12.3

14.4

tENZL

Enable Pad Z to Low

16.1

19.0

tENHZ

Enable Pad High to Z

9.8

11.5

tENLZ

Enable Pad Low to Z

11.5

13.6

tGLH

G to Pad High

12.4

14.6

tGHL

G to Pad Low

15.5

18.2

dTLH

Delta Low to High

0.09

0.11

ns/pF

dTHL

Delta High to Low

0.17

0.20

ns/pF

CMOS Output Module Timing1

tDLH

Data to Pad High

14.0

16.5

tDHL

Data to Pad Low

11.7

13.7

tENZH

Enable Pad Z to High

12.3

14.4

tENZL

Enable Pad Z to Low

16.1

19.0

tENHZ

Enable Pad High to Z

9.8

11.5

tENLZ

Enable Pad Low to Z

11.5

13.6

tGLH

G to Pad High

12.4

14.6

tGHL

G to Pad Low

15.5

18.2

dTLH

Delta Low to High

0.17

0.20

ns/pF

dTHL

Delta High to Low

0.12

0.15

ns/pF

Notes:

Delays based on 50 pF loading.

SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at

http://www.actel.com/appnotes.

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