DSPIC33FJ64GS406 datasheet(188/456 Pages) MICROCHIP

188 / 456 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591E-page 188

 2009-2012 Microchip Technology Inc.

FIGURE 9-1:

OSCILLATOR SYSTEM DIAGRAM

÷ N

ACLK

SELACLK

APSTSCLR<2:0>

To PWM/ADC(1)

ENAPLL

ASRCSEL

FRCSEL

POSCCLK

FRCCLK

÷ N

ROSEL RODIV<3:0>

REFCLKO(3)

POSCCLK

Reference Clock Generation

Auxiliary Clock Generation

Note 1:

See Section 9.1.3 “PLL Configuration” and Section 9.2 “Auxiliary Clock Generation” for configuration restrictions.

If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M

 must be connected.

REFCLKO functionality is not available if the primary oscillator is used.

The term, FP, refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this

document, FP and FCY are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode

is used in any ratio other than 1:1, which is the default.

FVCO(1)

FOSC

Secondary Oscillator (SOSC)

LPOSCEN

SOSCO

SOSCI

Timer 1

OSC2

OSC1

Primary Oscillator (POSC)

XTPLL, HSPLL,

XT, HS, EC

FRCDIV<2:0>

WDT, PWRT,

FSCM

FRCDIVN

SOSC

FRCDIV16

ECPLL, FRCPLL

NOSC<2:0>

FNOSC<2:0>

Reset

FRC

Oscillator

LPRC

Oscillator

DOZE<2:0>

S1/S3

FRC

LPRC

÷ 16

Clock Switch

Clock Fail

÷ 2

TUN<5:0>

PLL(1)

FCY(4)

FOSC

FVCO(1)

To ADC and

Generator

R(2)

POSCMD<1:0>

POSCCLK

FP(4)

Auxiliary Clock

APLL(1)

x16

dsPIC33FJ64GS406 bảng dữ liệu(PDF) 188 Page - Microchip Technology

dsPIC33FJ64GS406 bảng dữ liệu(HTML) 188 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL