DSPIC33FJ64GS406 datasheet(187/456 Pages) MICROCHIP

187 / 456 page

 2009-2012 Microchip Technology Inc.

DS70591E-page 187

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

9.0

OSCILLATOR

CONFIGURATION

The oscillator system provides:

• External and Internal Oscillator Options as Clock

Sources

• An On-Chip Phase-Locked Loop (PLL) to Scale

the Internal Operating frequency to the Required

System Clock Frequency

• An Internal FRC Oscillator that can also be used

with the PLL, thereby allowing Full-Speed Operation

without any External Clock Generation Hardware

• Clock Switching Between Various Clock Sources

• Programmable Clock Postscaler for System

Power Savings

• A Fail-Safe Clock Monitor (FSCM) that Detects

Clock Failure and takes Fail-Safe Measures

• A Clock Control Register (OSCCON)

• Nonvolatile Configuration bits for Main Oscillator

Selection

• Auxiliary PLL for ADC and PWM

A simplified diagram of the oscillator system is shown

in Figure 9-1.

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610

families of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to Section 42. “Oscillator

(Part IV)” (DS70307) in the “dsPIC33F/

PIC24H Family Reference Manual”,

which is available from the Microchip web

site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

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