DSPIC33FJ64GS406 datasheet(180/456 Pages) MICROCHIP

180 / 456 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591E-page 180

 2009-2012 Microchip Technology Inc.

DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER

R/W-0

U-0

FORCE(1)

—

bit 15

bit 8

U-0

R/W-1

—

IRQSEL<6:0>(2)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

FORCE: Force DMA Transfer bit(1)

1 = Forces a single DMA transfer (Manual mode)

0 = Automatic DMA transfer initiation by DMA request

bit 14-7

Unimplemented: Read as ‘0’

bit 6-0

IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2)

0000000-1111111 = DMAIRQ0-DMAIRQ127 are selected to be Channel DMAREQ

Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced

DMA transfer is complete.

2: See Table 8-1 for a complete listing of IRQ numbers for all interrupt sources.

DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A

R/W-0

STA<15:8>

bit 15

bit 8

R/W-0

STA<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-0

STA<15:0>: Primary DMA RAM Start Address bits (source or destination)

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