DSPIC33FJ64GS406 datasheet(177/456 Pages) MICROCHIP

177 / 456 page

 2009-2012 Microchip Technology Inc.

DS70591E-page 177

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

8.0

DIRECT MEMORY ACCESS

(DMA)

Direct Memory Access (DMA) is a very efficient

mechanism of copying data between peripheral SFRs

(e.g., the UART Receive register and Input Capture 1

buffer) and buffers or variables stored in RAM, with

minimal CPU intervention. The DMA Controller

(DMAC) can automatically copy entire blocks of data

without requiring the user software to read or write the

peripheral Special Function Registers (SFRs) every

time a peripheral interrupt occurs. The DMA Controller

uses a dedicated bus for data transfers and, therefore,

does not steal cycles from the code execution flow of

the CPU. To exploit the DMA capability, the

corresponding user buffers or variables must be

located in DMA RAM.

The peripherals that can utilize DMA are listed in

Table 8-1 along with their associated Interrupt Request

(IRQ) numbers.

TABLE 8-1:

DMA CONTROLLER CHANNEL TO PERIPHERAL ASSOCIATIONS

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610

family of devices. However, it is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to Section 22.

“Direct

Memory

Access

(DMA)”

(DS70182) in the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note:

The DMA module is not available on

dsIPC33FJ32GS406/606/608/610 and

dsPIC33FJ64GS406 devices.

Peripheral to DMA Association

DMAxREQ Register

IRQSEL<6:0> Bits

DMAxPAD Register

Values to Read from

Peripheral

DMAxPAD Register

Values to Write to

Peripheral

INT0 – External Interrupt 0

0000000

——

IC1 – Input Capture 1

0000001

0x0140 (IC1BUF)

—

IC2 – Input Capture 2

0000101

0x0144 (IC2BUF)

—

IC3 – Input Capture 3

0100101

0x0148 (IC3BUF)

—

IC4 – Input Capture 4

0100110

0x014C (IC4BUF)

—

OC1 – Output Compare 1 Data

0000010

—

0x0182 (OC1R)

OC1 – Output Compare 1 Secondary Data

0000010

—

0x0180 (OC1RS)

OC2 – Output Compare 2 Data

0000110

—

0x0188 (OC2R)

OC2 – Output Compare 2 Secondary Data

0000110

—

0x0186 (OC2RS)

OC3 – Output Compare 3 Data

0011001

—

0x018E (OC3R)

OC3 – Output Compare 3 Secondary Data

0011001

—

0x018C (OC3RS)

OC4 – Output Compare 4 Data

0011010

—

0x0194 (OC4R)

OC4 – Output Compare 4 Secondary Data

0011010

—

0x0192 (OC4RS)

TMR2 – Timer2

0000111

——

TMR3 – Timer3

0001000

——

TMR4 – Timer4

0011011

——

TMR5 – Timer5

0011100

——

SPI1 – Transfer Done

0001010

0x0248 (SPI1BUF)

SPI2 – Transfer Done

0100001

0x0268 (SPI2BUF)

UART1RX – UART1 Receiver

0001011

0x0226 (U1RXREG)

—

UART1TX – UART1 Transmitter

0001100

—

0x0224 (U1TXREG)

UART2RX – UART2 Receiver

0011110

0x0236 (U2RXREG)

—

UART2TX – UART2 Transmitter

0011111

—

0x0234 (U2TXREG)

ECAN1 – RX Data Ready

0100010

0x0640 (C1RXD)

—

ECAN1 – TX Data Request

1000110

—

0x0642 (C1TXD)

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