DSPIC33FJ64GS406 datasheet(324/456 Pages) MICROCHIP

324 / 456 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591E-page 324

 2009-2012 Microchip Technology Inc.

bit 12-8

TRGSRC3<4:0>: Trigger 3 Source Selection bits(1)

Selects trigger source for conversion of analog channels AN7 and AN6.

11111 = Timer2 period match

11110 = PWM Generator 8 current-limit ADC trigger

11101 = PWM Generator 7 current-limit ADC trigger

11100 = PWM Generator 6 current-limit ADC trigger

11011 = PWM Generator 5 current-limit ADC trigger

11010 = PWM Generator 4 current-limit ADC trigger

11001 = PWM Generator 3 current-limit ADC trigger

11000 = PWM Generator 2 current-limit ADC trigger

10111 = PWM Generator 1 current-limit ADC trigger

10110 = PWM Generator 9 secondary trigger is selected

10101 = PWM Generator 8 secondary trigger is selected

10100 = PWM Generator 7 secondary trigger is selected

10011 = PWM Generator 6 secondary trigger is selected

10010 = PWM Generator 5 secondary trigger is selected

10001 = PWM Generator 4 secondary trigger is selected

10000 = PWM Generator 3 secondary trigger is selected

01111 = PWM Generator 2 secondary trigger is selected

01110 = PWM Generator 1 secondary trigger is selected

01101 = PWM secondary special event trigger is selected

01100 = Timer1 period match

01011 = PWM Generator 8 primary trigger is selected

01010 = PWM Generator 7 primary trigger is selected

01001 = PWM Generator 6 primary trigger is selected

01000 = PWM Generator 5 primary trigger is selected

00111 = PWM Generator 4 primary trigger is selected

00110 = PWM Generator 3 primary trigger is selected

00101 = PWM Generator 2 primary trigger is selected

00100 = PWM Generator 1 primary trigger is selected

00011 = PWM special event trigger is selected

00010 = Global software trigger is selected

00001 = Individual software trigger is selected

00000 = No conversion is enabled

bit 7

IRQEN2: Interrupt Request Enable 2 bit

1 = Enables IRQ generation when requested conversion of Channels AN5 and AN4 is completed

0 = IRQ is not generated

bit 6

PEND2: Pending Conversion Status 2 bit

1 = Conversion of Channels AN5 and AN4 is pending; set when selected trigger is asserted

0 = Conversion is complete

bit 5

SWTRG2: Software Trigger 2 bit

1 = Starts conversion of AN5 and AN4 (if selected by TRGSRC bits)(1)

This bit is automatically cleared by hardware when the PEND2 bit is set.

0 = Conversion has not started

ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED)

Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other

conversions are in progress, the conversion is performed when the conversion resources are available.

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