DSPIC33FJ64GS406 datasheet(310/456 Pages) MICROCHIP

310 / 456 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591E-page 310

 2009-2012 Microchip Technology Inc.

22.3

Module Functionality

The High-Speed, 10-Bit ADC is designed to support

power conversion applications when used with the

High-Speed PWM module. The ADC may have one or

two SAR modules, depending on the device variant. If

two SARs are present on a device, two conversions

can be processed at a time, yielding 4 Msps conversion

rate. If only one SAR is present on a device, only one

conversion can be processed at a time, yielding 2 Msps

conversion rate. The High-Speed, 10-Bit ADC produces

two 10-bit conversion results in a 0.5 microsecond.

The ADC module supports up to 24 external analog

inputs and two internal analog inputs. To monitor

reference voltage, two internal inputs, AN24 and AN25,

are connected to EXTREF and INTREF, respectively.

The analog reference voltage is defined as the device

supply voltage (AVDD/AVSS).

The ADC module uses the following control and status

registers:

• ADCON: ADC Control Register

• ADSTAT: ADC Status Register

• ADBASE: ADC Base Register(1,2)

• ADPCFG: ADC Port Configuration Register

• ADPCFG2: ADC Port Configuration Register 2

• ADCPC0: ADC Convert Pair Control Register 0

• ADCPC1: ADC Convert Pair Control Register 1

• ADCPC2: ADC Convert Pair Control Register 2

• ADCPC3: ADC Convert Pair Control Register 3

• ADCPC4: ADC Convert Pair Control Register 4

• ADCPC5: ADC Convert Pair Control Register 5

• ADCPC6: ADC Convert Pair Control Register 6(2)

The ADCON register controls the operation of the

ADC module. The ADSTAT register displays the

status of the conversion processes. The ADPCFG

registers configure the port pins as analog inputs or

as digital I/O. The ADCPCx registers control the

triggering of the ADC conversions. See Register 22-1

through Register 22-12 for detailed bit configurations.

Note:

A unique feature of the ADC module is its

ability to sample inputs in an asynchro-

nous manner. Individual sample and hold

circuits can be triggered independently of

each other.

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