AD8115AST datasheet(18/32 Pages) AD

18 / 32 page

AD8114/AD8115

Rev. B | Page 18 of 32

THEORY OF OPERATION

The AD8114 (G = 1) and AD8115 (G = 2) are crosspoint arrays

with 16 outputs, each of which can be connected to any one of

16 inputs. Organized by output row, 16 switchable

transconductance stages are connected to each output buffer in

the form of a 16-to-1 multiplexer. Each of the 16 rows of

transconductance stages are wired in parallel to the 16 input

pins, for a total array of 256 transconductance stages. Decoding

logic for each output selects one (or none) of the

transconductance stages to drive the output stage. The

transconductance stages are NPN-input differential pairs,

sourcing current into the folded cascode output stage. The

compensation network and emitter follower output buffer are in

the output stage. Voltage feedback sets the gain, with the

AD8114 configured as a unity gain follower, and the AD8115

configured as a gain-of-2 amplifier with a feedback network.

This architecture provides drive for a reverse-terminated video

load (150 Ω), with low differential gain and phase error for

relatively low power consumption. Power consumption is

further reduced by disabling outputs and transconductance

stages that are not in use. The user will notice a small increase

in input bias current as each transconductance stage is enabled.

Features of the AD8114 and AD8115 simplify the construction

of larger switch matrices. The unused outputs of both devices

can be disabled to a high impedance state, allowing the outputs

of multiple ICs to be bused together. In the case of the AD8115,

a feedback isolation scheme is used so that the impedance of the

gain-of-2 feedback network does not load the output. Because

no additional input buffering is necessary, high input resistance

and low input capacitance are easily achieved without

additional signal degradation. To control enable glitches, it is

recommended that the disabled output voltage be maintained

within its normal enabled voltage range (±3.3 V). If necessary,

the disabled output can be kept from drifting out of range by

applying an output load resistor to ground.

A flexible TTL-compatible logic interface simplifies the

programming of the matrix. Both parallel and serial loading

into a first rank of latches programs each output. A global latch

simultaneously updates all outputs. A power-on reset pin is

available to avoid bus conflicts by disabling all outputs.

APPLICATIONS

The AD8114/AD8115 have two options for changing the

programming of the crosspoint matrix. In the first option a

serial word of 80 bits can be provided that will update the entire

matrix each time. The second option allows for changing a

single output’s programming via a parallel interface. The serial

option requires fewer signals, but more time (clock cycles) for

changing the programming, while the parallel programming

technique requires more signals, but can change a single output

at a time and requires fewer clock cycles to complete

programming.

Serial Programming

The serial programming mode uses the device pins CE, CLK,

DATA IN, UPDATE, and SER/PAR. The first step is to assert a

low on SER/PAR to enable the serial programming mode. CE

for the chip must be low to allow data to be clocked into the

device. The CE signal can be used to address an individual

device when devices are connected in parallel.

The UPDATE signal should be high during the time that data is

shifted into the device’s serial port. Although the data will still

shift in when UPDATE is low, the transparent, asynchronous

latches will allow the shifting data to reach the matrix. This will

cause the matrix to try to update to every intermediate state as

defined by the shifting data.

The data at DATA IN is clocked in at every down edge of CLK.

A total of 80 bits must be shifted in to complete the

programming. For each of the 16 outputs, there are four bits

(D0 to D3) that determine the source of its input followed by

one bit (D4) that determines the enabled state of the output. If

D4 is low (output disabled), the four associated bits (D0 to D3)

do not matter because no input will be switched to that output.

The most significant output address data is shifted in first, and

then following in sequence until the least significant output

address data is shifted in. At this point UPDATE can be taken

low, which will cause the programming of the device according

to the data that was just shifted in. The UPDATE registers are

asynchronous, and when UPDATE is low (and CE is low), they

are transparent.

AD8115AST bảng dữ liệu(PDF) 18 Page - Analog Devices

AD8115AST bảng dữ liệu(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

bảng dữ liệu tải về

Link URL