AD8115AST datasheet(10/32 Pages) AD

10 / 32 page

AD8114/AD8115

Rev. B | Page 10 of 32

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Pin Description

58, 60, 62, 64, 66, 68, 70, 72,

4, 6, 8, 10, 12, 14, 16, 18

INxx

Analog Inputs. xx = Channels 00 through 15.

DATA IN

Serial Data Input, TTL Compatible.

CLK

Clock, TTL Compatible. Falling edge triggered.

DATA OUT

Serial Data Out, TTL Compatible.

UPDATE

Enable (Transparent) Low. Allows serial register to connect directly to switch matrix.

Data latched when high.

100

RESET

Disable Outputs, Active Low.

Chip Enable, Enable Low. Must be low to clock in and latch data.

SER/PAR

Selects Serial Data Mode, Low or Parallel Data Mode, High. Must be connected.

53, 51, 49, 47, 45, 43, 41, 39,

37, 35, 33, 31, 29, 27, 25, 23

OUTyy

Analog Outputs. yy = Channels 00 through 15.

3, 5, 7, 9, 11, 13, 15, 17, 19, 57,

59, 61, 63, 65, 67, 69, 71, 73

AGND

Analog Ground for Inputs and Switch Matrix. Must be connected.

1, 75

DVCC

+5 V for Digital Circuitry.

2, 74

DGND

Ground for Digital Circuitry.

20, 56

AVEE

−5 V for Inputs and Switch Matrix.

21, 55

AVCC

+5 V for Inputs and Switch Matrix.

54, 50, 46, 42, 38, 34, 30, 26, 22

AVCCxx/yy

+5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.

52, 48, 44, 40, 36, 32, 28, 24

AVEExx/yy

–5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.

Parallel Data Input, TTL Compatible (output select LSB).

Parallel Data Input, TTL Compatible (output select).

Parallel Data Input, TTL Compatible (output select MSB).

Parallel Data Input, TTL Compatible (input select LSB)

Parallel Data Input, TTL Compatible (input select).

Parallel Data Input, TTL Compatible (input select MSB).

Parallel Data Input, TTL Compatible (output enable).

85 to 93

No Connect.

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