AD8115AST datasheet(5/32 Pages) AD

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AD8114/AD8115

Rev. B | Page 5 of 32

TIMING CHARACTERISTICS (SERIAL)

Table 2. Timing Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Serial Data Setup Time

CLK Pulse Width

100

Serial Data Hold Time

CLK Pulse Separation, Serial Mode

100

CLK to UPDATE Delay

UPDATE Pulse Width

CLK to DATA OUT Valid, Serial Mode

200

Propagation Delay, UPDATE to Switch On or Off

–

Data Load Time, CLK = 5 MHz, Serial Mode

–

µs

CLK, UPDATE Rise and Fall Times

–

100

RESET Time

–

200

Table 3. Logic Levels

VIH

VIL

VOH

VOL

IIH

IIL

IOH

IOL

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

DATA OUT

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

DATA OUT

2.0 V min

0.8 V max

2.7 V min

0.5 V max

20 µA max

−400 µA min

−400 µA max

3.0 mA min

LOAD DATA INTO

SERIAL REGISTER

ON FALLING EDGE

DATA IN

CLK

1 = LATCHED

0 = TRANSPARENT

DATA OUT

OUT7 (D4)

OUT7 (D3)

OUT00 (D0)

TRANSFER DATA FROM SERIAL

LATCHES DURING LOW LEVEL

UPDATE

Figure 2. Timing Diagram, Serial Mode

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