MPC2605ZP66 datasheet(3/30 Pages) MOTOROLA

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MPC2605

MOTOROLA

PIN DESCRIPTIONS

Pin Locations

Pin Name

Type

Description

19G, 17H – 19H, 17J – 19J,

17K – 19K, 17L – 19L,

17M – 19M, 17N – 19N,

17P – 19P, 17R – 19R,

18T, 19T, 18U, 19U,

18V, 19V, 18W

A0 – A31

I/O

Address inputs from processor. Can also be outputs for processor snoop

addresses. A0 is the MSB. A31 is the LSB.

AACK

I/O

Address acknowledge input/output.

ABB

I/O

Used as an input to qualify bus grants. Driven as an output during address tenure

initiated by the MPC2605.

17C – 19C, 17D

AP0 – AP3

I/O

Address parity.

19B

APE

Address parity error. When an address parity error is detected, APE will be driven

low one clock cycle after the assertion of TS then High–Z following clock cycle.

18E

APEN

Address parity enable. When tied low, enables address parity bits and the

address parity error bit.

ARTRY

I/O

Address retry status I/O. Generated when a read or write snoop to a dirty

processor cache line has occurred.

17E

CFG0

CFG1

CFG2

CFG3

CFG4

Configuration inputs. These must be tied to either VDD or VSS.

CFG0

CFG1

CFG2

256KB

512KB; A26 = 0

512KB; A26 = 1

1MB; A25 – A26 = 00

1MB; A25 – A26 = 01

1MB; A25 – A26 = 10

1MB; A25 – A26 = 11

CFG3

Snoop Data Tenure Selector

Supports snoop data tenure

Does not support snoop data tenure

CFG4

AACK Driver Enable

Disable AACK driver

Enable AACK driver

I/O

Cache inhibit I/O.

CLK

Clock input. This must be the same as the processor clock input.

CPU BG

CPU bus grant input.

CPU2 BG

MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor

configuration as the second CPU BG.

CPU3 BG

MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor

configuration as the third CPU BG.

CPU4 BG

MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor

configuration as the fourth CPU BG.

CPU BR

CPU bus request input.

CPU2 BR

MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor

configuration as the second CPU BR.

CPU3 BR

MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor

configuration as the third CPU BR.

CPU4 BR

MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor

configuration as the fourth CPU BR.

CPU DBG

CPU data bus grant input from arbiter.

CPU2 DBG

MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor

configuration as the second CPU DBG.

CPU3 DBG

MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor

configuration as the third CPU DBG.

* See pin diagram (page 2) for specific pin assignment of these bus signals.

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