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MPC2605ZP66 bảng dữ liệu(PDF) 24 Page - Motorola, Inc

tên linh kiện MPC2605ZP66
Giải thích chi tiết về linh kiện  Integrated Secondary Cache for PowerPC Microprocessors
PDF  30 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MPC2605ZP66 bảng dữ liệu(HTML) 24 Page - Motorola, Inc

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MPC2605
MOTOROLA
24
JTAG
AC OPERATING CONDITIONS AND CHARACTERISTICS
FOR THE TEST ACCESS PORT (IEEE 1149.1)
(TJ = 20 to + 110°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
3 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Measurement Timing Level
1.5 V
. . . . . . . . . . . . . . . . . . . . . . .
Output Load
50
Ω Termination to 1.5 V
. . . . . . . . . . . . . . . . . . . . . . . .
TAP CONTROLLER TIMING
P
Sb l
MPC2605–66
Ui
N
Parameter
Symbol
Min
Max
Unit
Notes
Cycle Time
tCK
30
—
ns
Clock High Time
tCKH
12
—
ns
1
Clock Low Time
tCKL
12
—
ns
1
Clock Low to Output Valid
tA
5
9
ns
Clock Low to Output High–Z
tCKZ
0
9
ns
2
Clock Low to Output Active
tCKX
0
9
ns
3, 4
Setup Times:
TMS
TDI
ts
tsd
2
—
ns
1
Hold Times:
TMS
TDI
th
thd
2
—
ns
1
NOTES:
1. This parameter is sampled and not 100% tested.
2. TDO will High–Z from a clock low edge depending on the current state of the TAP state machine.
3. TDO is active only in the SHIFT–IR and SHIFT–DR state of the TAP state machine.
4. Transition is measured
± 500 mV from steady–state voltage. This parameter is sampled and not 100% tested.
TDI TEST
DATA IN
TCK TEST
CLOCK
tCK
TDO TEST
DATA OUT
tH
tCKX
tSD
tS
tHD
tA
tCKZ
TMS TEST
MODE SELECT
tCKH
tCKL
Figure 10. TAP Controller Timing



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