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74ABT16652CSSC bảng dữ liệu(PDF) 2 Page - Fairchild Semiconductor |
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74ABT16652CSSC bảng dữ liệu(HTML) 2 Page - Fairchild Semiconductor |
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2 / 9 page ![]() www.fairchildsemi.com 2 Functional Description In the transceiver mode, data present at the HIGH imped- ance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamen- tal bus-management functions that can be performed with the ABT16652. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPABn, CPBAn) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simulta- neously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH imped- ance state, each set of bus lines will remain at its last state. Note A: Real-Time Transfer Bus B to Bus A Note B: Real-Time Transfer Bus A to Bus B Note C: Storage Note D: Transfer Storage Data to A or B FIGURE 1. OEAB 1 OEBA 1 CPAB 1 CPBA 1 SAB 1 SBA 1 LL X X X L OEAB 1 OEBA 1 CPAB 1 CPBA 1 SAB 1 SBA 1 HH X X L X OEAB 1 OEBA 1 CPAB 1 CPBA 1 SAB 1 SBA 1 XH XX X LX X XX LH XX OEAB 1 OEBA 1 CPAB1 CPBA 1 SAB 1 SBA 1 H L H or L H or L H H |
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