OR2C04A datasheet(165/192 Pages) ETC

165 / 192 page

Data Sheet

June 1999

ORCA Series 2 FPGAs

Lucent Technologies Inc.

165

Timing Characteristics (continued)

Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN.

Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input on DIN

Figure 70. Slave Serial Configuration Mode Timing Diagram

Table 52A. OR2CxxA/OR2TxxA Slave Serial Configuration Mode Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C

Parameter

Symbol

Min

Max

Unit

DIN Setup Time

—

DIN Hold Time

0—

CCLK High Time

TCH

—

CCLK Low Time

TCL

—

CCLK Frequency

—10

MHz

CCLK to DOUT

—30

Table 52B. OR2TxxB Slave Serial Configuration Mode Timing Characteristics

OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Max

Unit

DIN Setup Time

—

DIN Hold Time

0—

CCLK High Time

TCH

12.5

—

CCLK Low Time

TCL

12.5

—

CCLK Frequency

—40

MHz

CCLK to DOUT

—10

5-4535(F)

DIN

CCLK

DOUT

TCL

TCH

BIT N

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