ADMC401BST datasheet(59/60 Pages) AD

59 / 60 page

ADMC401

–59–

REV. B

SPORT1_SCLKDIV (R/W)

DM (0x3FF1)

SPORT1_RFSDIV (R/W)

DM (0x3FF0)

RBUF

RECEIVE AUTOBUFFER ENABLE

TBUF

TRANSMIT AUTOBUFFER ENABLE

RMREG

RECEIVE M REGISTER

RIREG

RECEIVE I REGISTER

TMREG

TRANSMIT M REGISTER

TIREG

TRANSMIT I REGISTER

XTALDELAY

4096 CYCLE DELAY ENABLE

1 = DELAY, 0 = NO DELAY

PDFORCE

POWERDOWN FORCE

PUCR

POWERUP CONTEXT RESET ENABLE

1 = SOFT RESET (CONTEXT CLEAR),

0 = RESUME EXECUTION

SPORT1_AUTOBUF_CTRL (R/W)

DM (0x3FEF)

SPORT1_CTRL_REG (R/W)

FLAG OUT (READ ONLY)

IINTERNAL SERIAL CLOCK GENERATION ISCLK

RECEIVE FRAME SYNC REQUIRED RFSR

RECEIVE FRAME SYNC WIDTH RFSW

TRANSMIT FRAME SYNC REQUIRED TFSR

TRANSMIT FRAME SYNC WIDTH TFSW

ITFS INTERNAL TRANSMIT FRAME SYNC ENABLE

SLEN SERIAL WORD LENGTH

DTYPE DATA FORMAT

00 = RIGHT JUSTIFY, ZERO-FILLED UNUSED MSBS

01 = RIGHT JUSTIFY, SIGN EXTEND INTO UNUSED MSBS

10 = COMPAND USING

-LAW

11 = COMPAND USING A-LAW

9876543210

INVRFS IINVERT RECEIVE FRAME SYNC

INVTFS INVERT TRANSMIT FRAME SYNC

IRFS INTERNAL RECEIVE FRAME SYNC ENABLE

DM (0x3FF2)

Figure 47. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.

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