PCAL9535APW datasheet(13/46 Pages) NXP

13 / 46 page

PCAL9535A

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Product data sheet

Rev. 1 — 28 September 2012

13 of 46

NXP Semiconductors

PCAL9535A

Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O

6.3 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a

high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the

Output port register. In this case, there are low-impedance paths between the I/O pin and

either VDD or VSS. The external voltage applied to this I/O pin should not exceed the

recommended levels for proper operation.

6.4 Power-on reset

When power (from 0 V) is applied to VDD, an internal power-on reset holds the

PCAL9535A in a reset condition until VDD has reached VPOR. At that time, the reset

condition is released and the PCAL9535A registers and I2C-bus/SMBus state machine

initializes to their default states. After that, VDD must be lowered to below VPORF and back

up to the operating voltage for a power-reset cycle. See Section 8.3 “Power-on reset

requirements”.

At power-on reset, all registers return to default values.

Fig 6.

Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)

INTERRUPT

MASK

VDD

P0_0 to P0_7

P1_0 to P1_7

output port

configuration

data from

shift register

write

configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

002aah428

data from

shift register

VSS

to INT

PULL-UP/PULL-DOWN

CONTROL

ESD

protection

diode

100 kΩ

VDD

ESD

protection

diode

input port

latch

LATCH

read pulse

input latch

data from

shift register

write input

latch pulse

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