PCAL9535APW datasheet(12/46 Pages) NXP

12 / 46 page

PCAL9535A

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Product data sheet

Rev. 1 — 28 September 2012

12 of 46

NXP Semiconductors

PCAL9535A

Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O

6.2.11 Interrupt status register pair (4Ch, 4Dh)

These read-only registers are used to identify the source of an interrupt. When read, a

logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0

indicates that the input pin is not the source of an interrupt.

When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt

status bit will return logic 0. A register pair write is described in Section 7.1 and a register

pair read is described in Section 7.2.

6.2.12 Output port configuration register (4Fh)

The output port configuration register selects port-wise push-pull or open-drain I/O stage.

A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 6). A logic 1

configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended

command sequence to program this register (4Fh) before the configuration registers (06h,

07h) sets the port pins as outputs.

ODEN0 configures Port 0_x and ODEN1 configures Port 1_x.

Table 25.

Interrupt status port 0 register (address 4Ch) bit description

Bit

Symbol

S0.7

S0.6

S0.5

S0.4

S0.3

S0.2

S0.1

S0.0

Default

Table 26.

Interrupt status port 1 register (address 4Dh) bit description

Bit

Symbol

S1.7

S1.6

S1.5

S1.4

S1.3

S1.2

S1.1

S1.0

Default

Table 27.

Output port configuration register (address 4Fh)

Bit

Symbol

reserved

ODEN1

ODEN0

Default

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