PCAL9535APW datasheet(22/46 Pages) NXP

22 / 46 page

PCAL9535A

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Product data sheet

Rev. 1 — 28 September 2012

22 of 46

NXP Semiconductors

PCAL9535A

Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O

Reducing the current drive capability may be desirable to reduce system noise. When the

output switches (transitions from H/L), there is a peak current that is a function of the

output drive selection. This peak current runs through VDD and VSS package inductance

and will create noise (some radiated, but more critically Simultaneous Switching Noise

(SSN)). In other words, switching many outputs at the same time will create ground and

supply noise. The output drive strength control through the Current Control registers

allows the user to mitigate SSN issues without the need of additional external

components.

8.3 Power-on reset requirements

In the event of a glitch or data corruption, PCAL9535A can be reset to its default

conditions by using the power-on reset feature. Power-on reset requires that the device

go through a power cycle to be completely reset. This reset also happens when the device

is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 17 and Figure 18.

Table 28 specifies the performance of the power-on reset feature for PCAL9535A for both

types of power-on reset.

Fig 17. VDD is lowered below 0.2 V or to 0 V and then ramped up to VDD

Fig 18. VDD is lowered below the POR threshold, then ramped back up to VDD

002aah329

VDD

time

ramp-up

ramp-down

(dV/dt)r

(dV/dt)f

re-ramp-up

(dV/dt)r

time to re-ramp

when VDD drops

below 0.2 V or to VSS

td(rst)

002aah330

VDD

time

ramp-down

(dV/dt)f

ramp-up

(dV/dt)r

time to re-ramp

when VDD drops

to VPOR(min) − 50 mV

td(rst)

VI drops below POR levels

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