PIC24FJ128GA310 datasheet(94/406 Pages) MICROCHIP

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PIC24FJ128GA310 FAMILY

DS39996F-page 94

 2010-2011 Microchip Technology Inc.

TABLE 7-3:

RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

7.4.1

POR AND LONG OSCILLATOR

START-UP TIMES

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) will have a relatively long

start-up time. Therefore, one or more of the following

conditions is possible after SYSRST is released:

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has not expired (if a

crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

The device will not begin to execute code until a valid

clock source has been released to the system. There-

fore, the oscillator and PLL start-up delays must be

considered when the Reset delay time must be known.

7.4.2

FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

If the FSCM is enabled, it will begin to monitor the

system clock source when SYSRST is released. If a

valid clock source is not available at this time, the

device will automatically switch to the FRC oscillator

and the user can switch to the desired crystal oscillator

in the Trap Service Routine (TSR).

Reset Type

Clock Source

SYSRST Delay

System Clock

Delay

Notes

POR

TPOR + TSTARTUP + TRST

—

1, 2, 3

ECPLL

TPOR + TSTARTUP + TRST

TLOCK

1, 2, 3, 5

XT, HS, SOSC

TPOR + TSTARTUP + TRST

TOST

1, 2, 3, 4, 8

XTPLL, HSPLL

TPOR + TSTARTUP + TRST

TOST + TLOCK

1, 2, 3, 4, 5, 8

FRC, FRCDIV

TPOR + TSTARTUP + TRST

TFRC

1, 2, 3, 6, 7

FRCPLL

TPOR + TSTARTUP + TRST

TFRC + TLOCK

1, 2, 3, 5, 6

LPRC

TPOR + TSTARTUP + TRST

TLPRC

1, 2, 3, 6

BOR

TSTARTUP + TRST

—

2, 3

ECPLL

TSTARTUP + TRST

TLOCK

2, 3, 5

XT, HS, SOSC

TSTARTUP + TRST

TOST

2, 3, 4, 8

XTPLL, HSPLL

TSTARTUP + TRST

TOST + TLOCK

2, 3, 4, 5, 8

FRC, FRCDIV

TSTARTUP + TRST

TFRC

2, 3, 6, 7

FRCPLL

TSTARTUP + TRST

TFRC + TLOCK

2, 3, 5, 6

LPRC

TSTARTUP + TRST

TLPRC

2, 3, 6

MCLR

Any Clock

TRST

—

WDT

Any Clock

TRST

—

Software

Any clock

TRST

—

Illegal Opcode

Any Clock

TRST

—

Uninitialized W

Any Clock

TRST

—

Trap Conflict

Any Clock

TRST

—

Note 1:

TPOR = Power-on Reset delay (10

s nominal).

TSTARTUP = TVREG (10

s nominal when VREGS = 1 and when VREGS = 0; depends upon

WDTWIN<1:0> bits setting).

TRST = Internal State Reset time (2

s nominal).

TOST = Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing

the oscillator clock to the system.

TLOCK = PLL lock time.

TFRC and TLPRC = RC oscillator start-up times.

If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC

so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid. It switches to the

primary oscillator after its respective clock delay.

TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the

oscillator clock to the system.

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