ACT8600 datasheet(7/50 Pages) ACTIVE-SEMI

7 / 50 page

ACT8600

Rev 3, 15-Nov-12

Innovative Power

ActivePMU

TM and ActivePathTM are trademarks of Active-Semi.

2CTM is a trademark of NXP.

- 7 -

www.active-semi.com

PIN DESCRIPTIONS CONT’D

NAME

DESCRIPTION

SW4

Switch Node for REG4.

OUT4

REG4 Output.

No Connect.

OUT2

Output Voltage Sense for REG2.

VP2

Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed to the IC as

close as possible.

SW2

Switch Node for REG2.

GP12

Power Ground for REG1 and REG2. Connect GA, GP12 and GP3 together at a single point as

close to the IC as possible.

SW1

Switch Node for REG1.

VP1

Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed to the IC as

close as possible.

OUT1

Output Voltage Sense for REG1.

PWREN

Master enable pin.

nIRQ

Open-Drain Interrupt Output.

OUT10

REG10 Output. Bypass it to GA with a 0.47μF capacitor.

OUT9

REG9 Output. Bypass it to GA with a 1μF capacitor.

5VIN

5V Input pin for OTG switch (optionally from OUT4 or external 5V source).

VBUS

USB VBUS.

CHGIN

Power Input for the Battery Charger. Bypass CHGIN to GA with a capacitor placed as close to

the IC as possible. The battery charger is automatically enabled when a valid voltage is present

on CHGIN .

38, 39

VSYS

System Output Pins. Bypass to GA with a 10μF or larger ceramic capacitor.

Exposed Pad. Must be soldered to ground on PCB.

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