AD1843JS datasheet(27/64 Pages) AD

27 / 64 page

AD1843

REV. 0

–27–

GNDD

VDD

LEFT

RIGHT

LEFT

RIGHT

VCC

ADC

µ/A

LAW

CONTROL AND STATUS REGISTERS

CRA0, CRA1, CRA25, CRA26,

CRA27, CRA28

RESET

PWRDWN

∑

MUTE

ATTN

∑

MUTE

∑

FIFO

µ/A

LAW

SCLK

SDFS

SDI

SDO

TSO

TSI

XCTL [1:0]

PDMNFT

CLOCK GENERATION

CLKOUT

XTALI

XTALO SYNC3 SYNC2 SYNC1 CONV3 CONV2 CONV1

BIT3

BIT2

BIT1

CRA15, CRA16, CRA17, CRA18, CRA19,

CRA20, CRA21, CRA22, CRA23, CRA24

AD1843

CRAX = CONTROL REGISTER ADDRESS “X”

CRA25

CRA12

CRA11

ATTN

MUTE

CRA13

ATTN

MUTE

CRA14

CRA26

DAC1

DAC2

CRA26

µ/A

LAW

FIFO

ATTN

Address

Clock Generator 1 Control—Mode

Clock Generator 1 Control—Sample Rate

Clock Generator 1 Control—Sample Phase Shift

Clock Generator 2 Control—Mode

Clock Generator 2 Control—Sample Rate

Clock Generator 2 Control—Sample Phase Shift

Clock Generator 3 Control—Mode

Clock Generator 3 Control—Sample Rate

Clock Generator 3 Control—Sample Phase Shift

Codec Configuration—Digital Filter and Mode Select

Codec Configuration—Serial Interface

Codec Configuration—Channel Power Down

Codec Configuration—Fundamental Settings

Reserved for Future Expansion

Figure 13. AD1843 Control Registers Associated with Block Diagram

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